NON-VOLATILE MEMORY BASED SYNCHRONOUS LOGIC

摘要

A method for setting resistance states of a first and a second resistive memory element (RME) is disclosed. The method may include coupling, via a common node, a first RME to a second RME. The method may include setting the first RME to either a high voltage resistance state or a low voltage resistance state. The method may include setting the second RME to a different state relative to the state of the first RME, wherein setting the second RME is substantially simultaneous with setting the first RME.