| 发明名称 |
Reset dampener |
| 摘要 |
A memory reset system including a first memory socket and a second memory socket. A reset signal generator can generate a reset signal to the first memory socket. A dampener circuit can receive the reset signal from the reset signal generator and transmit a dampened reset signal to the second memory socket. |
| 申请公布号 |
US8843722(B2) |
申请公布日期 |
2014.09.23 |
| 申请号 |
US201012692980 |
申请日期 |
2010.01.25 |
| 申请人 |
Hewlett-Packard Development Company, L.P. |
发明人 |
Brooks Robert C. |
| 分类号 |
G06F12/00;G06F1/24;G06F13/40 |
主分类号 |
G06F12/00 |
| 代理机构 |
|
代理人 |
Hablinski Reed |
| 主权项 |
1. A memory reset system comprising:
a reset signal generator; an asynchronous dampener circuit to receive a reset signal initiated by the reset signal generator; and memory module sockets wherein the dampener circuit is between two memory module sockets, wherein the dampener circuit dampens noise generated at a memory module socket. |
| 地址 |
Houston TX US |
