发明名称 |
Semiconductor device |
摘要 |
A semiconductor device includes a multilayer substrate, a semiconductor element secured to an upper surface of the multilayer substrate, a first metal pattern located on a portion of a lower surface of the multilayer substrate, a dielectric having a higher permittivity than the multilayer substrate and located on the lower surface of the multilayer substrate, and a bottom surface electrode located on a bottom surface of the semiconductor device. The bottom surface electrode, the dielectric, and the first metal pattern together form a bypass capacitor. |
申请公布号 |
US8796817(B2) |
申请公布日期 |
2014.08.05 |
申请号 |
US201313975505 |
申请日期 |
2013.08.26 |
申请人 |
Mitsubishi Electric Corporation |
发明人 |
Okuda Toshio |
分类号 |
H01L23/48;H01L23/522 |
主分类号 |
H01L23/48 |
代理机构 |
Leydig, Voit & Mayer, Ltd. |
代理人 |
Leydig, Voit & Mayer, Ltd. |
主权项 |
1. A semiconductor device comprising:
a multilayer substrate having upper and lower surfaces and a permittivity; a semiconductor element secured to said upper surface of said multilayer substrate; an intra-substrate via that is connected electrically to said semiconductor element and located in said multilayer substrate, extending to said lower surface of said multilayer substrate; a first metal pattern located on a portion of said lower surface of said multilayer substrate; a second metal pattern in contact with a lower end of said intra-substrate via; a dielectric having a higher permittivity than the permittivity of said multilayer substrate and located on said lower surface of said multilayer substrate, covering said first and second metal patterns; a first intra-dielectric via located in said dielectric, connected at an upper end to said first metal pattern, and extending to a lower surface of said dielectric; a second intra-dielectric via located in said dielectric, connected at an upper end to said second metal pattern, and extending to said lower surface of said dielectric; a ground pattern connected to a lower end of said first intra-dielectric via; and a bottom surface electrode connected to a lower end of said second intra-dielectric via, wherein
a portion of said first metal pattern is disposed on said dielectric directly opposite a portion of said bottom surface electrode, andsaid bottom surface electrode, said dielectric, and said first metal pattern, together, constitute a bypass capacitor. |
地址 |
Tokyo JP |