发明名称 Redundancy loading efficiency
摘要 A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
申请公布号 US8799598(B2) 申请公布日期 2014.08.05
申请号 US201213399537 申请日期 2012.02.17
申请人 Spansion LLC 发明人 Ong Wei-Kent;Beh Jih-Hong;Lau Sei-Wei Henry;Ang Oon-Poh
分类号 G06F12/04;G06F12/14;G06F11/20;G06F12/16 主分类号 G06F12/04
代理机构 代理人
主权项 1. A method comprising: loading a first portion of a set of redundancy data into a register of a microcontroller for each redundant sector of a plurality of redundant sectors, wherein the register is loaded with a plurality of first portions of sets of redundancy data, a first portion of a set of redundancy data for each redundant sector; loading a second portion of the set of redundancy data into the register for each redundant sector of the plurality of redundant sectors, wherein the register is loaded with a plurality of second portions of redundancy data, a second portion of the set of redundancy data for each redundant sector, wherein loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
地址 Sunnyvale CA US