发明名称 System, Method and Computer-Readable Medium for Providing Selective Protection and Endurance Improvements in Flash-Based Cache
摘要 A cache controller includes a cache memory distributed across multiple solid-state storage units in which cache line fill operations are applied sequentially in a defined manner and write operations are protected by a RAID-5 (striping plus parity) scheme upon a stripe reaching capacity. The cache store is responsive to data from a storage controller managing a primary data store. The cache store arranges the data differently based on the origin or type of data received at the cache interface. Line fill operations are placed in the cache memory without generating and storing corresponding parity information. When a sufficient number of write operations fill strips that constitute a full stripe are present in cache store, a corresponding parity strip is generated and stored in a strip location designated for storage of the parity information.
申请公布号 US2014208005(A1) 申请公布日期 2014.07.24
申请号 US201314071702 申请日期 2013.11.05
申请人 LSI Corporation 发明人 Simionescu Horia;Baderdinni Anant;Bert Luca
分类号 G06F12/02 主分类号 G06F12/02
代理机构 代理人
主权项 1. A method for operating a cache memory supported by solid-state data storage modules, the method comprising: defining a layout for distributing data in a cache memory supported by N solid-state memory elements, where N is an integer; initializing, in a cache controller, a line fill count and a write count; receiving a data block in a cache interface, the contents of the data block designated for storage in the cache memory; determining, in a cache controller, if the content of the data block is presently stored in a primary data store coupled to the cache interface or if the content is from a host system in anticipation of a subsequent transfer to the primary data store; and when the content of the data block is presently stored in the primary data store, storing the data block in the cache memory in response to the line fill count and incrementing the line fill count, otherwise, storing the data block in the cache memory in response to the write count and incrementing the write count.
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