| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an event response control technology which realizes speeding up of data processing, and reducing of a burden on a CPU.SOLUTION: A data processor has a central processing unit (2) for executing a command, and a first to a third internal circuits which are controlled by the central processing unit. The first internal circuit is an interruption controller (13) which responds to an event signal supplied from the second internal circuit or the third internal circuit, and outputs an interruption request signal to the central processing unit. The second internal circuit is an event link controller (6) which responds to an event signal supplied from the first internal circuit or the third internal circuit, and outputs a start control signal to the third internal circuit. The third internal circuit is configured by a plurality of circuit modules, and can be controlled by the central processing unit and the event link controller in parallel.</p> |
