| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve highly accurate clock synchronization. <P>SOLUTION: This receiving-side node includes: a TS packet receiving part 711 being a receiving means for receiving a TS packet 120 that is periodically transmitted by a master node 700 being a transmitting side node; a PLL 712 being a phase synchronizing means for generating a frequency adjustment amount and a clock of a slave node 710 being a receiving-side node by a calculation based on a time stamp of the TS packet 120; a packet filter 713 for determining whether the absolute value of the frequency adjustment amount is equal to or smaller than a prescribed threshold, and adopting the TS packet 120 in which the absolute value of the frequency adjustment amount is equal to or smaller than the threshold; and a parameter controller 714 being a parameter control means for separately holding a parameter that is generated in the process of calculation by the PLL 712 and held by the PLL 712, and updating the parameter held by itself and the parameter held by the PLL 712 according to a determination result of the packet filter 713. <P>COPYRIGHT: (C)2010,JPO&INPIT |
