发明名称 |
CHANNEL CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME |
摘要 |
A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal. |
申请公布号 |
US2014181604(A1) |
申请公布日期 |
2014.06.26 |
申请号 |
US201313845254 |
申请日期 |
2013.03.18 |
申请人 |
SK HYNIX INC. |
发明人 |
KIM Ki Tae |
分类号 |
G01R31/3185 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
1. A channel control circuit having a plurality of channels, comprising:
a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal in response to the clock buffer control signal, wherein the clock output signal is used as an internal clock of a semiconductor device. |
地址 |
Icheon-si KR |