发明名称 |
Methods of fabricating semiconductor devices using a plasma process with non-silane gas including deuterium |
摘要 |
Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and forming a gate electrode on the gate oxide layer. An etch stop layer is formed on the gate oxide layer and the gate electrode. A plasma process is performed on the interface between the gate oxide layer and the substrate using a non-silane treatment gas including deuterium. An interlayer dielectric layer is formed on the etch stop layer. A bottom metal line is formed on the interlayer dielectric layer. |
申请公布号 |
US8741710(B2) |
申请公布日期 |
2014.06.03 |
申请号 |
US20080248431 |
申请日期 |
2008.10.09 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Shin Dong-Suk;Lee Ho;Kim Tae-Gyun |
分类号 |
H01L21/8238;H01L21/336 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
1. A method for fabricating a semiconductor device, the method comprising:
forming a gate oxide layer on a substrate and a gate electrode on the gate oxide layer, and forming a first spacer on opposite side walls of the gate electrode and a second spacer on each first spacer, and a low-concentration source/drain region arranged with the first spacer and a high-concentration source/drain region arranged with the second spacer; forming a silicide layer on the gate electrode and the high-concentration source/drain region; performing a preliminary plasma process on an interface between the gate oxide layer and the substrate after forming the silicide layer; forming an etch stop layer on a surface of the substrate; performing a plasma process on the interface between the gate oxide layer and the substrate after forming the etch stop layer; forming an interlayer dielectric layer on the etch stop layer; forming a contact hole which penetrates through the etch stop layer and the interlayer dielectric layer; performing a subsequent plasma process on the interface between the gate oxide layer and the substrate after forming the interlayer dielectric layer; and forming a bottom metal line on the interlayer dielectric layer, wherein the preliminary plasma process, the plasma process, and the subsequent plasma process are performed using a non-silane treatment gas including deuterium, and wherein the subsequent plasma process causes deuterium from a non-silane treatment gas in the contact hole to diffuse therefrom into the interface between the substrate and the gate oxide layer.
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地址 |
KR |