| 摘要 |
<p>An SRAM array and a manufacturing method thereof are disclosed. Each of SRAM cells comprises two pull-ups (PU), two pass gates (PG), and two pull-down (PD) FinFETs. PU transistors are adjacent each other and comprise one active fin having a first fin width. Each of the PU transistors shares one or more active fins with a PD transistor. The active fins which are shared by the PG and PD transistors have a second fin width smaller than the first fin width. The method comprises; a step of patterning multiple fins having the active fins and dummy fins; and a step of patterning a part of the dummy fins and patterning it. Any dummy fin is not arranged between PU finFETs within a memory cell. One dummy fin is arranged between the PU FinFET and the active fins which are shared by the PG and PD transistors. The dummy fins are arranged between adjacent memory cells.</p> |
