发明名称 LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS
摘要 Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate comprising a plurality of build-up layers, such as BBUL. In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
申请公布号 US2014138845(A1) 申请公布日期 2014.05.22
申请号 US201213684110 申请日期 2012.11.21
申请人 KULKARNI DEEPAK V.;MORTENSEN RUSSELL K.;GUZEK JOHN S. 发明人 KULKARNI DEEPAK V.;MORTENSEN RUSSELL K.;GUZEK JOHN S.
分类号 H01L23/498;H01L21/50 主分类号 H01L23/498
代理机构 代理人
主权项
地址
您可能感兴趣的专利