发明名称 Clock distribution circuit
摘要 A clock distribution circuit is provided with a clock generation circuit configured to generate a clock signal, a clock distribution network in which the clock signal is distributed, and a sequential circuit configured to operate on the clock signal distributed through a branch point of the clock distribution network. The clock distribution circuit is further provided with a clock generation circuit configured to input as a feedback signal the clock signal that has branched from the branch point and to output the clock signal to the clock distribution network based on the inputted feedback signal and a reference clock signal. The branch point is provided at a clock driver near the clock generation circuit, among preceding stage clock drivers of the sequential circuit of the clock distribution network.
申请公布号 US8710892(B2) 申请公布日期 2014.04.29
申请号 US201213597366 申请日期 2012.08.29
申请人 FUJIMORI KAZUYA;CANON KABUSHIKI KAISHA 发明人 FUJIMORI KAZUYA
分类号 H03K3/00 主分类号 H03K3/00
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