COMPUTING SYSTEM AND PROCESSOR WITH FAST POWER SURGE DETECTION AND INSTRUCTION THROTTLE DOWN TO PROVIDE FOR LOW COST POWER SUPPLY UNIT

摘要

A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.