发明名称 SINGLE WIRE BUS AND THREE WIRE BUS INTEROPERABILITY
摘要 PROBLEM TO BE SOLVED: To realize interoperability between existing serial bus interfaces and a single wire bus interface.SOLUTION: The output of a three wire interface is selected in a first mode, and the output of one or more single wire interfaces is selected in a second mode. In another aspect, a converter takes a single wire bus and produces signals according to a three wire interface. In yet another aspect, a termination symbol is inserted in a single wire interface signal, to facilitate conversion of the single wire interface signal and connection to a three wire interface. In yet another aspect, a strobe signal and/or a clock signal are generated in response to a detected start symbol. In yet another aspect, a strobe signal is deasserted and/or a clock signal is deasserted in response to a detected termination symbol.
申请公布号 JP2014041629(A) 申请公布日期 2014.03.06
申请号 JP20130205864 申请日期 2013.09.30
申请人 QUALCOMM INCORPORATED 发明人 HANSQUINE DAVID W;MUNEER MUHAMMAD ASIM
分类号 G06F13/42;G06F13/38 主分类号 G06F13/42
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