发明名称 SAMPLING CIRCUIT, INTEGRATION CIRCUIT AND A/D CONVERTER
摘要 PROBLEM TO BE SOLVED: To suppress a high frequency component of an input signal without hindering miniaturization of an electronic component.SOLUTION: A sampling circuit comprises sampling capacitors 105A_1, 105A_2 and 105B_1, 105B_2 for storing charges generated by an incoming input signal, and includes a plurality of switches 101A_1, 101A_2, 101B_1, 101B_2, 102A_1, 102A_2, 102B_1, 102B_2, 103A_1, 103A_2, 103B_1, 103B_2, 104A_1, 104A_2, 104B_1, 104B_2 for storing charges in the respective sampling capacitors. A circuit including the sampling capacitors 105A_1, 105A_2 and a circuit including 105B_1, 105B_2 are alternately operated, and the two circuits including the sampling capacitors alternately store the charges and alternately transfer the charges.
申请公布号 JP2014011556(A) 申请公布日期 2014.01.20
申请号 JP20120145576 申请日期 2012.06.28
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 NAKANISHI JUNYA
分类号 H03M1/08;H03M1/12 主分类号 H03M1/08
代理机构 代理人
主权项
地址