发明名称 ACCELERATING FUNCTIONAL VERIFICATION OF AN INTEGRATED CIRCUIT
摘要 Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.
申请公布号 US2014005992(A1) 申请公布日期 2014.01.02
申请号 US201213534189 申请日期 2012.06.27
申请人 DEINDL MICHAEL;RUEDINGER JEFFREY JOSEPH;ZOELLIN CHRISTIAN G. 发明人 DEINDL MICHAEL;RUEDINGER JEFFREY JOSEPH;ZOELLIN CHRISTIAN G.
分类号 G06G7/48 主分类号 G06G7/48
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