发明名称 |
Wafer Level Integrated Circuit Contactor and Method of Construction |
摘要 |
A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crows (40) are maintained relatively coplanar by the engagement of at least one flang (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner. |
申请公布号 |
US2013342233(A1) |
申请公布日期 |
2013.12.26 |
申请号 |
US201313921484 |
申请日期 |
2013.06.19 |
申请人 |
JOHNSTECH INTERNATIONAL CORPORATION |
发明人 |
EDWARDS JATHAN;MARKS CHARLES;HALVORSON BRIAN |
分类号 |
G01R1/073;G01R3/00 |
主分类号 |
G01R1/073 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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