| 摘要 |
A latch circuit (1) is equipped with: a PMOS transistor (10), the drain of which is connected to a first output node and the gate of which is connected to a second output node; a PMOS transistor (12), the drain of which is connected to the second output node and the gate of which is connected to the first output node; an NMOS transistor (14), the gate of which is connected to a first input node; an NMOS transistor (16), the gate of which is connected to a second input node; and an NMOS transistor (18), the gate of which is connected to a third input node.
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