发明名称 THREE DIMENSIONAL MEMORY CONTROL CIRCUITRY
摘要 An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
申请公布号 WO2013147743(A1) 申请公布日期 2013.10.03
申请号 WO2012US30632 申请日期 2012.03.26
申请人 INTEL CORPORATION;HELM, MARK;HOEI, JUNG SHENG;NGUYEN, DZUNG;YIP, AARON 发明人 HELM, MARK;HOEI, JUNG SHENG;NGUYEN, DZUNG;YIP, AARON
分类号 G11C7/10;G11C7/18;G11C8/14 主分类号 G11C7/10
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