发明名称 Universal parity encoder
摘要 A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.
申请公布号 US8533577(B1) 申请公布日期 2013.09.10
申请号 US201213555860 申请日期 2012.07.23
申请人 FENG WEISHI;YU ZHAN;MARVELL INTERNATIONAL LTD. 发明人 FENG WEISHI;YU ZHAN
分类号 G06F11/00 主分类号 G06F11/00
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