发明名称 Method of manufacturing NMOS transistor with low trigger voltage
摘要 A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.
申请公布号 US8507981(B2) 申请公布日期 2013.08.13
申请号 US201113271239 申请日期 2011.10.12
申请人 CHEN LU-AN;LAI TAI-HSIANG;TANG TIEN-HAO;UNITED MICROELECTRONICS CORP. 发明人 CHEN LU-AN;LAI TAI-HSIANG;TANG TIEN-HAO
分类号 H01L29/76;H01L31/062 主分类号 H01L29/76
代理机构 代理人
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