| 摘要 |
A first gate driver that drives a gate bus line corresponding to a first sub-pixel section and a second gate driver that drives a gate bus line corresponding to a second sub-pixel section are monolithically formed inside a panel. A shift register inside the second gate driver has a configuration where stages corresponding to respective rows and dummy stages each disposed for each row, are connected in series with one another. In such a configuration, a frequency of a clock signal for controlling an operation of the second gate driver is made twice as large as a frequency of a clock signal for controlling an operation of the first gate driver.
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