发明名称 |
INTEGRATED CIRCUIT DESIGN METHOD, DESIGN DEVICE AND PROGRAM |
摘要 |
PROBLEM TO BE SOLVED: To design an insulation recycling logic circuit so as to minimize power consumption.SOLUTION: An integrated circuit design method includes the steps of: grouping logic cells of an insulation recycling logic circuit into M (M≥N) logic cell subsets according to each logic depth; moving at least one logic cell of multiple grouped logic cells and changing a logic cell subset that at least includes the logic cell, so as to increase the number of logic cells included in at least one of the logic cell subsets; determining each logic cell set as one of the M logic cell subsets or as a sum set of two or more logic cell subsets; assigning N power clock signals to N logic cell sets determined; and determining each of the logic cell sets so that a logic cell included in at least one logic cell subset with the number of logic cells increased becomes a logic cell of a first stage in a logic cell set circuit. |
申请公布号 |
JP2013149122(A) |
申请公布日期 |
2013.08.01 |
申请号 |
JP20120009857 |
申请日期 |
2012.01.20 |
申请人 |
RENESAS ELECTRONICS CORP |
发明人 |
TANAKA KATSUNORI;NOGUCHI KOICHIRO;NOSE KOICHI |
分类号 |
G06F17/50;H01L21/82 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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