MODULATED CLOCK SYNCHRONIZER

摘要

The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1 - 2.2) comprising a number N of series connected clock delay elements (3.1 - 3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1 - 3.3) or elements of the at least one synchronizer (2.1 - 2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).