| 摘要 |
The present invention relates to a test arrangement for a serdes ip block and in particular provides a serdes test chip comprising a serdes instance to be tested and further instances of said serdes, said further instances constitution a data transfer path for data with which said serdes is to be tested. The data may come from a programmable gate array and enables the testing of data transfer schemes yet to be embodied in an integrated circuit ip block.
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