发明名称 HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY
摘要 In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period.
申请公布号 US2013181754(A1) 申请公布日期 2013.07.18
申请号 US201313784571 申请日期 2013.03.04
申请人 STMICROELECTRONICS PVT. LTD.;STMICROELECTRONICS PVT. LTD. 发明人 GUPTA NITIN
分类号 H03L7/199 主分类号 H03L7/199
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