发明名称 Post passivation interconnection schemes on top of IC chip
摘要 A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
申请公布号 US8482127(B2) 申请公布日期 2013.07.09
申请号 US20070856073 申请日期 2007.09.17
申请人 LIN MOU-SHIUNG;LEE JIN-YUAN;MEGICA CORPORATION 发明人 LIN MOU-SHIUNG;LEE JIN-YUAN
分类号 H01L23/48;H01L21/768;H01L23/528;H01L23/532;H01L23/60;H01L23/62;H01L27/02 主分类号 H01L23/48
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