发明名称 Electroplated posts with reduced topography and stress
摘要 Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.
申请公布号 US8476760(B2) 申请公布日期 2013.07.02
申请号 US201113288161 申请日期 2011.11.03
申请人 JAIN MANOJ K.;KODURI SREENIVASAN;TEXAS INSTRUMENTS INCORPORATED 发明人 JAIN MANOJ K.;KODURI SREENIVASAN
分类号 H01L23/48;H01L21/00;H01L21/44 主分类号 H01L23/48
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