| 摘要 |
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-back circuit is clocked on a rising clock edge of an input clock signal, while the second shift register loop-back signal is clocked on a negative edge of the input clock signal. The outputs of the first and second loop-back shift registers are ORed to provide a 50% duty cycle output clock signal.
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