发明名称
摘要 <p>Provided is a memory circuit including: memory cells (A) arranged in columns and rows; memory cells (B) each provided for each of the rows for storing information indicative of whether writing into the memory cells (A) of the each of the rows has been completed or not; and a circuit for selecting one of the rows by utilizing the information stored in the memory cells (B). The memory circuit writes information into the memory cell (B) upon completion of writing into the memory cells (A) of a given one of the rows. By utilizing a change in the information stored in the memory cell (B), the given one of the rows is switched from a selected state to a non-selected state, and a next row is switched from the non-selected state to the selected state so that writing is enabled. The operation is repeated to thereby sequentially select a row to be written.</p>
申请公布号 JP5208011(B2) 申请公布日期 2013.06.12
申请号 JP20090031380 申请日期 2009.02.13
申请人 发明人
分类号 G11C16/02;G11C16/06;G11C17/14 主分类号 G11C16/02
代理机构 代理人
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