发明名称 |
Communication systems, clock generation circuits thereof, and method for generating clock signal |
摘要 |
A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
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申请公布号 |
US8451971(B2) |
申请公布日期 |
2013.05.28 |
申请号 |
US20090407226 |
申请日期 |
2009.03.19 |
申请人 |
CHAO KUAN-HUA;LIU SHIUE-SHIN;TSAI JENG-HORNG;CHEN CHIH-CHING;LIU CHUAN;HSU TSE-HSIANG;MEDIATEK INC. |
发明人 |
CHAO KUAN-HUA;LIU SHIUE-SHIN;TSAI JENG-HORNG;CHEN CHIH-CHING;LIU CHUAN;HSU TSE-HSIANG |
分类号 |
H04L7/00;H03L7/06 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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