| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve an operation margin in a semiconductor device including a plurality of static type memory modules. <P>SOLUTION: The semiconductor device includes, for instance, a writing auxiliary circuit (for instance, WAST1[0]) for controlling a voltage level of a memory cell power source line (for instance, ARVDD[0]) connected to an SRAM memory cell MC to be written in a writing operation. The writing auxiliary circuit lowers the voltage level of the memory cell power source line to a predetermined voltage level (VM1) according to a writing auxiliary enable signal WTE to be validated in the writing operation, and controls the lowering speed at this time according to the pulse width of a writing auxiliary pulse signal WPT. The pulse width of the WPT is set to be made wider as the number of lines is increased (length of the memory cell power source line is longer). <P>COPYRIGHT: (C)2013,JPO&INPIT |
