发明名称 RATIONAL CLOCK DIVIDER FOR MEDIA TIMESTAMPS AND CLOCK RECOVERY FUNCTIONS
摘要 Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to drive software timer logic and generate media timestamps.
申请公布号 WO2012173962(A3) 申请公布日期 2013.04.11
申请号 WO2012US42007 申请日期 2012.06.12
申请人 INTEL CORPORATION;BROUILLETTE, PAT 发明人 BROUILLETTE, PAT
分类号 H04N21/242;H03L7/08;H04N21/2368 主分类号 H04N21/242
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