| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide techniques for debugging an integrated circuit. <P>SOLUTION: An integrated circuit 2 includes one or more transaction masters 8, 10, 12, 4 for issuing data transactions via interconnect circuitry 20. Debug access port circuitry is configured to respond to debug commands received from a debug controller 6 to generate barrier transactions which are issued to the interconnect circuitry. The interconnect circuitry responds to the received barrier transactions by constraining a relative ordering of at least some of the data transactions as they pass through the interconnect circuitry. <P>COPYRIGHT: (C)2013,JPO&INPIT |
