发明名称 METHOD FOR SYNCHRONOUS DETECTION AND SPEED CONTROL OF SERIAL INPUTS IN VESTIGIAL SIDEBAND MODULATOR
摘要 PURPOSE: A method for synchronous detection and speed control of serial inputs in a vestigial sideband(VSB) modulator is provided by detecting an MPEG synchronization and forming a VSB transmission format from the inputted MPEG transmission stream. CONSTITUTION: A method for synchronous detection and speed control of serial inputs in a vestigial sideband(VSB) modulator comprises the steps of: detecting an inputted MPEG transmission stream and storing the stream in FIFO; detecting a synchronization by reading the FIFO with a bit clock and forming a VSB transmission format by reading data with a byte clock; and transmitting the data having the VSB transmission format to a VSB processor.
申请公布号 KR20000025289(A) 申请公布日期 2000.05.06
申请号 KR19980042313 申请日期 1998.10.09
申请人 HYUNDAI ELECTRONICS IND. CO., LTD. 发明人 KIM, JU SANG
分类号 H04N7/52;H04N21/2383;(IPC1-7):H04N7/52 主分类号 H04N7/52
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