发明名称 Designing supply wirings in semiconductor integrated circuit by detecting power supply wiring of specific wiring layer in projection area
摘要 A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.
申请公布号 US8347253(B2) 申请公布日期 2013.01.01
申请号 US201213528369 申请日期 2012.06.20
申请人 FUJITSU SEMICONDUCTOR LIMITED;KUMAGAI KENJI;SUDA JUN 发明人 KUMAGAI KENJI;SUDA JUN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址
您可能感兴趣的专利