| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a layout structure of an SRAM memory cell, which can inhibit asymmetry failure in device property of a pair transistor. <P>SOLUTION: A first memory cell includes an inverter 41 in a unit arrangement region 1a and an inverter 81 in a unit arrangement region 1b. The inverters 41, 81 are both arranged on the lower side in the unit arrangement regions 1a, 1b, respectively. Accordingly, a direction from a source to a drain in a load transistor pair TP1, TP2 and a direction from a source to a drain in a drive transistor pair TN1, TN2 are the same. Further gate electrodes 31, 71 extend linearly and has no bent part. <P>COPYRIGHT: (C)2013,JPO&INPIT |
