| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a bit error rate at a receiving circuit in a transmission system using multi-phase clocks by taking signal at a stable reception signal condition. <P>SOLUTION: A receiving circuit includes a multi-phase clock generation circuit 51 which can generate a plurality of clocks having predetermined number of different phases and generates multi-phase clocks corresponding to the number of clock phases for receiving signal where the number of the phase is equal to or less than the predetermined number, acquisition circuits 25B and 25D for acquiring a received signal with the multi-phase clocks, phase detection circuits 44A to 44P for detecting phase differences between the received signal and the multi-phase clocks, an evaluation circuit 56 which extracts an amount of phase adjustment of the multi-phase clock which suits for acquiring received signal based on the detected phase differences, and a phase adjustment circuit 53 which adjusts a multi-phase reception clock phase according to the extracted amount of phase adjustment. <P>COPYRIGHT: (C)2012,JPO&INPIT |
