摘要 |
The invention relates to a circuit arrangement (5) for forming a digital interface (120, 121, 122, 123) comprising a digital data bus (123), which exchanges data when microprocessor systems are connected, wherein said data exchange can be effected bidirectionally. On transmission of data the circuit arrangement generates as bus master a bus clock speed and operates on receipt of data as a bus slave in accordance with a received clock signal. The circuit arrangement comprises at least one FIFO memory (101) for transmitting data and/or at least one FIFO memory (104) for receiving data. |
申请人 |
CONTINENTAL TEVES AG & CO. OHG;WEGENER, BASTIAN;KABULEPA, LUKUSA DIDIER;HARTMANN, RALF;BITSCH, CHRISTIAN |
发明人 |
WEGENER, BASTIAN;KABULEPA, LUKUSA DIDIER;HARTMANN, RALF;BITSCH, CHRISTIAN |