| 摘要 |
A cache memory is operated in a write through system, and an operation to be performed when a cache mishit occurs is performed when corresponding data is not stored in the cache memory, or only when an error occurs although there is the data. Then, a bit indicating that a soft error has occurred before is set in the cache memory, and when the bit indicates “1” and if an error has occurred again, it is determined that a hardware error has occurred, and an interrupt is generated in the CPU. The bit is to be reset at time intervals sufficiently shorter than the frequency at which it is considered that a soft error occurs. |
