| 摘要 |
Feedback circuits with DC offset cancellation are described. In an exemplary design, a feedback circuit includes a slow integrator and a summer. The slow integrator receives a first intermediate signal at a particular point in the feedback circuit and provides a second intermediate signal. The summer is located after the particular point and receives and sums the first and second intermediate signals to reduce DC offset in the first intermediate signal. In one design, the feedback circuit may be a delta-sigma (&Dgr;&Sgr;) modulator with at least one integrator coupled in cascade. The slow integrator is coupled to the output of the last integrator, receives the first intermediate signal from the last integrator, and provides the second intermediate signal. The summer is coupled to the last integrator and the slow integrator and sums the first and second intermediate signals to reduce DC offset in the first intermediate signal. |
