| 摘要 |
PURPOSE: A via-hole formation method for a penetration electrode is provided to improve reliability of a package manufacturing process by preventing generation of a notching phenomenon on a lower side surface part of a via-hole. CONSTITUTION: An etch-stop layer(110) is formed on the front surface of a silicon wafer(100). A first via-hole(115) which exposes the etch-stop layer on a first region of the silicon wafer is formed. A second via-hole(117a) is formed on a second region of the silicon wafer. A sidewall protection layer which exposes the surface of the silicon wafer of the bottom surface of the second via-hole is formed. Silicon of the bottom surface of the exposed second via-hole is etched with the sidewall protection layer as an etching barrier film. The sidewall protection layer is removed.
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