Receiver, interleaving and deinterleaving circuit and method

摘要

A framer circuit is provided with a FAS search block (901) being configured for performing two searches, a first search (941) for a first part of a sequence of framing bits, and a second search (942) for a second part of said sequence of framing bits, said first and second parts together forming said sequence of framing bits. The framer circuit may comprise a framer supervision block (902) configured to provide a shift signal on a shift interface (310), wherein the FAS search block (901) may be configured to provide information to the framer supervision block (902) about the position of the FAS.