发明名称 LSI test apparatus, LSI test method, and computer product
摘要 An LSI test apparatus includes a test circuit synthesizing unit that synthesizes a test circuit and inserts the test circuit in a pre-test-synthesis net list; a test pattern generating unit that, based on a post-test-synthesis net list acquired by the test circuit synthesizing unit, generates a test pattern that simultaneously activates selected gated clock buffers; a simulating unit that, using the test pattern generated by the test pattern generating unit, simulates operation of a circuit created from the post-test-synthesis net list; and a power source analyzing unit that analyzes voltage drop in terms of amount, based on operation rate information acquired by the simulating unit.
申请公布号 US8134383(B2) 申请公布日期 2012.03.13
申请号 US20070525427 申请日期 2007.02.20
申请人 YOSHIKAWA SATORU;FUJITSU SEMICONDUCTOR LIMITED 发明人 YOSHIKAWA SATORU
分类号 G01R31/26 主分类号 G01R31/26
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