| 摘要 |
An image processing apparatus includes a data output control unit to output image data on a line-by-line basis in response to a line synchronizing signal, and a data output interface circuit to transfer via a bus the image data that is output from the data output control unit on a line-by-line basis in response to the line synchronizing signal, wherein the data output interface circuit makes a transition, together with the bus, from a normal state to a power saving state when a predetermined check period next following completion of transfer, by the data output interface circuit, of image data for one line output from the data output control unit passes before transfer of image data for a next one line, and returns, together with the bus, from the power saving state to the normal state for transfer of image data for the next one line. |
