发明名称 |
VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF |
摘要 |
A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator. |
申请公布号 |
US2011310690(A1) |
申请公布日期 |
2011.12.22 |
申请号 |
US20100820712 |
申请日期 |
2010.06.22 |
申请人 |
HUANG MING-CHIEH;CHERN CHAN-HONG;YANG TIEN CHUN;LIN CHIH-CHANG;SWEI YUWEN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUANG MING-CHIEH;CHERN CHAN-HONG;YANG TIEN CHUN;LIN CHIH-CHANG;SWEI YUWEN |
分类号 |
G11C5/14 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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