发明名称 CIRCUIT, CONTROL SYSTEM, CONTROL METHOD, AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To provide a circuit capable of attaining high-speed frequency follow-up performance while satisfying jitter/wander suppression performance. <P>SOLUTION: The circuit detects and analyses a jitter/wander component and a frequency sudden change state based on phase comparison data of a PLL part 100 that reproduces a clock of an SDH (Synchronous Digital Hierarchy) signal and an Ethernet signal from an OTN (Optical Transport Network) signal, and controls a loop gain of the PLL part 100 based on the result. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011254122(A) 申请公布日期 2011.12.15
申请号 JP20090070347 申请日期 2009.03.23
申请人 NEC CORP;NEC COMMUN SYST LTD 发明人 TAKAHASHI MASAYUKI;YOSHIHARA TOMOKI
分类号 H03L7/093;H03L7/095;H03L7/107 主分类号 H03L7/093
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