| 摘要 |
The present disclosure describes implementations for performing register accesses and operations in a graphics processing apparatus. In one implementation, a graphics processing apparatus comprises an execution unit for processing programmed shader operations, wherein the execution unit is configured for processing operations of a plurality of threads. The apparatus further comprises memory forming a register file that accommodates all register operations for all the threads executed by the execution unit, the memory being organized in a plurality of banks, with a first plurality of banks being allocated to a first plurality of the threads and a second plurality of banks being allocated to the remaining threads. In addition, the apparatus comprises address translation logic configured to translate logical register identifiers into physical register addresses.
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