发明名称 Impedance adjustment circuit
摘要 An impedance adjustment circuit according to the present invention includes a first input buffer which detects that an input signal exceeds VREFA, a second input buffer which detects that the input signal exceeds VREFB, VREFB being higher than VREFA, a counter circuit A which performs count based on an output from the first input buffer, a counter circuit B which performs count based on an output from the second input buffer, and a termination resistor control circuit which controls impedance of a termination resistor provided in a termination of a transmission path based on the count in the counter circuit A and the count in the counter circuit B.
申请公布号 US8040150(B2) 申请公布日期 2011.10.18
申请号 US20100788957 申请日期 2010.05.27
申请人 RENESAS ELECTRONICS CORPORATION 发明人 NAKATSU ISAO
分类号 H03K17/16;G11C7/10;H03K19/003 主分类号 H03K17/16
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