| 摘要 |
A synchronous buck converter operates in a PWM mode of operation and switches to light-load mode of operation under a light-load condition. When operating in the light-load mode, the synchronous buck converter transitions between a burst mode and an idle mode of operation. In the burst mode of operation, the converter operates with a fixed but increased duty ratio, with respect to the PWM mode of operation, that installs additional energy in an output capacitor. In the idle mode of operation, the high-side and low-side transistors are each turned off. To maximize energy savings and to quickly transition back to the PWM mode of operation if the load increases, a limit as to the number of allowed switching cycles when bursting is imposed and a minimum ratio of the number of clock cycles when idling to the number of switching cycles when bursting is set. Additionally, a comparator is provided to detect a sudden step-increase in the load to quickly switch the converter back to the PWM mode of operation.
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